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NXP Semiconductors
PCU9955
16-channel UFm I 2 C-bus 57 mA constant current LED driver
7.3.8 OFFSET — LEDn output delay offset register
Table 12. OFFSET - LEDn output delay offset register (address 3Ah) bit description
Legend: * default value.
Address
3Ah
Register
OFFSET
Bit
7:4
3:0
Access
-
W only
Value
0000*
1000*
Description
not used
LEDn output delay offset factor
The PCU9955 can be programmed to have turn-on delay between LEDn outputs. This
helps to reduce peak current for the V DD supply and reduces EMI.
The order in which the LEDn outputs are enabled will always be the same (channel 0 will
enable first and channel 15 will enable last).
OFFSET control register bits [3:0] determine the delay used between the turn-on times as
follows:
0000 = no delay between outputs (all on, all off at the same time)
0001 = delay of 1 clock cycle (125 ns) between successive outputs
0010 = delay of 2 clock cycles (250 ns) between successive outputs
0011 = delay of 3 clock cycles (375 ns) between successive outputs
:
1111 = delay of 15 clock cycles (1.875 ? s) between successive outputs
Example: If the value in the OFFSET register is 1000 the corresponding delay =
8 ? 125 ns = 1 ? s delay between successive outputs.
channel 0 turns on at time 0 ? s
channel 1 turns on at time 1 ? s
channel 2 turns on at time 2 ? s
channel 3 turns on at time 3 ? s
channel 4 turns on at time 4 ? s
channel 5 turns on at time 5 ? s
channel 6 turns on at time 6 ? s
channel 7 turns on at time 7 ? s
channel 8 turns on at time 8 ? s
channel 9 turns on at time 9 ? s
channel 10 turns on at time 10 ? s
channel 11 turns on at time 11 ? s
channel 12 turns on at time 12 ? s
channel 13 turns on at time 13 ? s
channel 14 turns on at time 14 ? s
channel 15 turns on at time 15 ? s
PCU9955
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 October 2012
? NXP B.V. 2012. All rights reserved.
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